Because logic elements, such as AND gates and OR gates, are heavily utilized for processing information, the speed of such gates significantly affects the overall processing speed. Therefore, a common goal of integrated circuit designs is to provide increased processing speed.
In FIG. 1 is illustrated a conventional positive-logic AND gate structure, implemented in Complementary Metal-Oxide-Semiconductor (CMOS) technology. In positive logic, a "logical zero" is indicated by a first reference voltage V.sub.0 (also commonly represented as V.sub.SS) that is less than a second reference voltage V.sub.1 (also commonly represented as V.sub.DD), which is representative of a "logical one". In negative logic, the voltage V.sub.0 of a logical zero is greater than the voltage V.sub.1 of a logical one. A logical zero is also referred to herein as a "low" signal and a logical one is also referred to herein as a "high" signal.
The following two general design rules are useful in the design of CMOS circuits. First Design Rule: each MOS stage inverts logic. This rule follows inherently from the structure of MOS gates. The practical implication of this rule is that noninverting logic requires an even number of stages. Second Design Rule: n-channel transistors are utilized to conduct logical zero signals and p-channel transistors are utilized to conduct logical one signals. If a particular CMOS circuit violates this rule, it will draw an undue amount of power. The reason for this is that a high voltage V.sub.1, applied to a p-channel, depletion-mode MOS field effect transistor, does not completely turn off such a transistor when a low voltage V.sub.0 is applied to its source. Similarly, a low voltage V.sub.0, applied to an n-channel, enhancement-mode MOS field effect transistor, does not completely turn off such a transistor when a high voltage V.sub.1 is applied to its drain.
FIG. 1 illustrates a conventional, positive logic AND gate 10. A pair of p-channel transistors 11 and 12 are connected in parallel between the high voltage source, of voltage V.sub.1, and an intermediate signal node 13. A pair of n-channel transistors 14 and 15 are connected in series between the low voltage source, of voltage V.sub.0, and the intermediate signal node 14. The gate electrodes of transistors 11 and 15 are connected to a first input 16 on which is applied a first digital control signal A.sub.1. The gate electrodes of transistors 12 and 14 are connected to a second input 17 on which is applied a second digital control signal A.sub.2. Elements 11-17 function as a NAND gate and represent the first stage 18 of this AND gate. Therefore, this circuit includes a second stage 19 that functions as an inverter to convert this circuit into an AND gate. This second stage includes: a p-channel MOS transistor-110 connected between the high voltage source of voltage V.sub.1 and an output signal port 111; and an n-channel MOS transistor 112 connected between output signal port 111 and the low voltage source of voltage V.sub.0.
FIG. 2 illustrates a conventional, positive logic OR gate 20. A pair of p-channel transistors 21 and 22 are connected in series between the high voltage source, of voltage V.sub.1, and an intermediate signal node 23. A pair of n-channel transistors 24 and 25 are connected in parallel between the low voltage source, of voltage V.sub.0, and the intermediate signal node 24. The gate electrodes of transistors 21 and 25 are connected to a first input 26 on which is applied a first digital control signal A.sub.1. The gate electrodes of transistors 22 and 24 are connected to a second input 27 on which is applied a second digital control signal A.sub.2. Elements 21-27 function as a NOR gate and represent the first stage 28 of this OR gate. Therefore, this circuit includes a second stage 29 that functions as an inverter to convert this circuit into an AND gate. This second stage includes: a p-channel MOS transistor 210 connected between the high voltage source of voltage V.sub.1 and an output signal port 211; and an n-channel MOS transistor 212 connected between output signal port 211 and the low voltage source of voltage V.sub.0.
Unfortunately, in both of these logic circuits, in response to a change in either or both of input signals A.sub.1 and A.sub.2, the output signal Z changes only after the period, equal to two gate delays, required for the effects of such change in A.sub.1 and/or A.sub.2 to ripple through the two stages of these two circuits. It would be advantageous to have AND gate and OR gate circuit designs that do not introduce at most one gate delay between the change of a signal on one of the input nodes and the resulting change in the output signal on the output signal port. It is also important that such circuit not require an undue amount of power.